Abstract—Miniaturization has been a constant challenge to
meet the demands of high performance, high density, lower power, and lower
voltage complex devices. Miniaturization is the main drive force for the
migration from micro electronic device structures to nano electronic device
structures. Planar CMOS scaling has been delivering better performance &
low power devices at each cutting edge of the technology node for more than three
decades. Now, CMOS scaling is facing crucial limitations and some show stoppers
are affecting bulk CMOS scaling. So, Semiconductor industry is witnessing the
phase-out of Planar CMOS with the introduction of new device architecture like 3D
FinFET technology for extending the Moore’s Law for Nanoscale technologies. This
paper discusses the evolution of Planar CMOS technology, CMOS Scaling
challenges, Planar CMOS Optimization technologies & the next generation
Nano architectures in order to extend the scaling beyond planar CMOS. FinFET is
emerging technology beyond 22nm. This paper studies FinFET architecture, advantages
and manufacturing challenges associated with it. It also throws light on future
technologies like Carbon nanotube, Silicon Nanowire FET and Tunneling FET etc.

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